7476 IC Dual Master-Slave J-K Flip-Flops DIP-16

74
76 IC Dual Master-Slave J-K Flip-Flops

The 7476 is a dual master-slave J-K flip-flop integrated circuit in a 16-pin DIP package. Each of the two flip-flops features separate J and K inputs, a clock input, and asynchronous preset and clear inputs, allowing independent control and initialization. On the rising (or falling, depending on the variant) edge of the clock, the master captures the J/K inputs, while the slave outputs are then updated, preventing race conditions. The outputs include both Q and Q (not-Q), providing complementary signals. Thanks to its master-slave architecture, the 7476 avoids the unstable race behavior seen in simpler J-K circuits. This makes it suitable for use in counters, registers, sequential logic circuits, and digital control systems where edge-triggered, bistable storage is needed.

Features

Contains two independent J-K master-slave flip-flops in a single 16-pin package.

Provides both Q and Q (complementary outputs) for each flip-flop.

Equipped with asynchronous preset and clear inputs for direct setting or resetting.

Operates with edge-triggered clocking to prevent race conditions.

Compatible with standard TTL logic levels.

High noise immunity and reliable switching performance.

Designed with master-slave architecture for stable operation.

Standard DIP-16 package, easy for prototyping and PCB integration.

Widely used in counters, registers, shift storage, and sequential logic systems.

Pin Layout

Pin Configuration

Pin Number

Pin Name

Description

5

Vcc

Powers the IC typically with 5V

13

Ground

Connected to the ground of the system

JK Flip Flop 1 / JK Flip Flop 2

1,6

Clock-1/ Clock-2

These pins must be provided with a clock pulse for the flip-flop

2,7

Preset-1 / Preset-2

When the Preset is high the flip flop will set Q=1 and not Q=0

3, 8

Clear-1/Clear-2

When Clear is high the flip flop will set Q=0 and not Q=1

12,16

K-1/ K-2

Input pin of the Flip Flop

4,9

J-1 / J-2

Another Input pin of the Flip Flop

10,14

Q-1(bar) / Q-2 (bar)

The inverted output pin of Flip Flop

11,15

Q-1 / Q-2

Output Pin of the Flip Flop

Specifications

Parameter

Typical Value

Conditions / Notes

V_CC (supply voltage)

5.0 V

Nominal operating voltage

V_IH (min input HIGH voltage)

2.0 V

For J, K, Clock, Preset, Clear

V_IL (max input LOW voltage)

0.8 V

Input low level threshold

V_OH (min output HIGH voltage)

~ 2.73.5 V

Depends on loading (pull-up, fan-out)

V_OL (max output LOW voltage)

~ 0.2 V

With standard load conditions

Propagation delay, t_PLH / t_PHL

~ 2050 ns

From Clock to outputs, depending on load

Input leakage current (I_I)

20 A

Typical input leakage for J, K, Preset, Clear

Operating temperature range

0 to 70 C (commercial)

Standard ambient range

Applications

Frequency division.

Binary counters.

Shift registers.

Toggle flip-flop applications.

Digital memory elements.

State machines.

Pulse synchronization.

Debouncing circuits.

Control circuits.

Package Contents

1 x
7476 IC Dual Master-Slave J-K Flip-Flops DIP-16

Datasheet

7476